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1 ds05-10156-4e fujitsu semiconductor data sheet memory cmos 256k 16 bit fast page mode dynamic ram mb814260-60/-70 cmos 262,144 16 bit fast page mode dynamic ram n description the fujitsu mb814260 is a fully decoded cmos dynamic ram (dram) that contains 4,194,304 memory cells accessible in 16-bit increments. the mb814260 features a ?ast page mode of operation whereby high-speed access of up to 512 16-bits of data can be selected in the same row. the mb814260-60/-70 drams are ideally suited for memory applications such as embedded control, buffer, portable computers, and video imaging equipment where very low power dissipation and high bandwidth are basic requirements of the design. the mb814260 is fabricated using silicon gate cmos and fujitsus advanced four-layer polysilicon process. this process, coupled with three-dimensional stacked capacitor memory cells, reduces the possibility of soft errors and extends the time interval between memory refreshes. n absolute maximum ratings (see note.) note: permanent device damage may occur if the above absolute maximum ratings are exceeded. functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. exposure to absolute maximum rating conditions for extended periods may affect device reliability. parameter symbol value unit voltage at any pin relative to v ss v in , v out ?.5 to +7 v voltage of v cc supply relative to v ss v cc ?.5 to +7 v power dissipation p d 1.0 w short circuit output current 50 ma storage temperature t stg ?5 to +125 c temperature under bias t bias 0 to +70 c this device contains circuitry to protect the inputs against damage due to high static voltages or electric ?lds. however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high impedance circuit.
2 mb814260-60/MB814260-70 n product line & features n package parameter mb814260-60 MB814260-70 ras access time 60 ns max. 70 ns max. cas access time 20 ns max. 20 ns max. address access time 30 ns max. 35 ns max. random cycle time 110 ns max. 125 ns min. fast page mode cycle time 40 ns min. 45 ns min. low power dissipation operating current 523 mw max. 462 mw max. standby current 11 mw max. (ttl level)/5.5 mw max. (cmos level) 262,144 words 16 bit organization silicon gate, cmos, advanced stacked capaci- tor cell all input and output are ttl comaptible 512 refresh cycles every 8.2 ms 9 rows 9 columns, addressing scheme 1we / 2cas early write or oe controlled write capability ras only cas -before-ras , or hidden refresh fast page mode, read-modify-write capability on chip substrate bias generator for high performance package and ordering information ?40-pin plastic (400 mil) soj, order as mb814260- pj ?44-pin plastic (400 mil) tsop-ii with normal bend leads, order as mb814260- pftn ?44-pin plastic (400 mil) tsop-ii with reverse bend leads, order as mb814260- pftr plastic soj package lcc-40p-m01 fpt-44p-m07 (normal bend) fpt-44p-m08 (reverse bend) marking side marking side plastic tsop packages
3 mb814260-60/MB814260-70 n capacitance (t a = 25 c, f = 1 mhz) parameter symbol typ. max. unit input capacitance, a 0 to a 8 c in1 ?pf input capacitance, ras , lcas , ucas , we , oe c in2 ?pf input/output capacitance, dq 1 to dq 16 c dq ?pf we ras lcas ucas clock gen #1 write clock gen mode control clock gen #2 column decoder sense ampl & i/o gate 4,194,304 bit storage cell data in buffer data out buffer address buffer pre- decoder refresh address counter row decoder a0 a1 a2 a3 a4 a5 a6 a7 a8 substrate bias gen dq1 to dq16 & oe fig. 1 ? mb814260 dynamic ram - block diagram v cc v ss
4 mb814260-60/MB814260-70 n pin assignments and descriptions 40-pin soj: (top view) 44-pin fpt: (top view) v cc dq 1 dq 2 dq 3 dq 4 v cc dq 5 dq 6 dq 7 dq 8 nc. nc. we ras nc. a 0 a 1 a 2 a 3 v cc v cc dq 1 dq 2 dq 3 dq 4 v cc dq 5 dq 6 dq 7 dq 8 1 2 3 4 5 9 10 11 12 13 14 6 7 8 15 16 17 18 19 20 27 28 38 37 36 35 34 30 29 33 32 31 40 39 26 25 24 23 22 21 1 2 3 4 5 9 10 6 7 8 13 14 15 16 17 18 19 20 21 22 32 31 30 29 28 27 26 25 24 23 44 43 42 41 40 39 38 37 36 35 32 31 30 29 28 27 26 25 24 23 44 43 42 41 40 39 38 37 36 35 1 2 3 4 5 9 10 6 7 8 13 14 15 16 17 18 19 20 21 22 (making side) (making side) 1 pin index 1 pin index designator function dq 1 to dq 16 v cc a 0 to a 8 v ss data input/ output write enable row address strobe. +5 volt power supply. lower column address strobe circuit ground. output enable. upper column address strobe ras lcas ucas we oe v ss dq 16 dq 15 dq 14 dq 13 v ss dq 12 dq 11 dq 10 dq 9 nc. lcas ucas oe a 8 a 7 a 6 a 5 a 4 v ss v ss dq 16 dq 15 dq 14 dq 13 v ss dq 12 dq 11 dq 10 dq 9 nc. nc. we ras nc. a 0 a 1 a 2 a 3 v cc nc. lcas ucas oe a 8 a 7 a 6 a 5 a 4 v ss v cc dq 1 dq 2 dq 3 dq 4 v cc dq 5 dq 6 dq 7 dq 8 v ss dq 16 dq 15 dq 14 dq 13 v ss dq 12 dq 11 dq 10 dq 9 nc. nc. we ras nc. a 0 a 1 a 2 a 3 v cc nc. lcas ucas oe a 8 a 7 a 6 a 5 a 4 v ss address inputs. row : a 0 to a 8 column : a 0 to a 8 refresh : a 0 to a 8
5 mb814260-60/MB814260-70 n recommended operating conditions * : undershoots of up to ?.0 volts with a pulse width not exceeding 20 ns are acceptable. n functional operation address inputs eighteen input bits are required to decode any sixteen of 4,194,304 cell addresses in the memory matrix. since only nine address bits are available, the column and row inputs are separately strobed by lcas or ucas and ras as shown in figure 5. first, nine row address bits are input on pins a 0 -through-a 8 and latched with the row address strobe (ras ) then, nine column address bits are input and latched with the column address strobe ( lcas or ucas ). both row and column addresses must be stable on or before the falling edges of ras and lcas or ucas , respectively. the address latches are the ?w-through type; thus, address information appearing after t rah (min)+ t t is automatically treated as the column address to start select operation of the column decode. therefore, to have correct data within t rac , the column address should be input within t rad (max.). if t rad > t rad (max.), the access time is the later one of either t aa or t cas . write enable the read or write mode is determined by the logic state of we . when we is active low, a write cycle is initiated; when we is high, a read cycle is selected. during the read mode, input data are ignored. when an early write cycle is executed, the output buffers stay in a high-impedance state during the cycle. data input input data are written into memory in either of three basic ways?he early write cycle, the oe (delayed) write cycle, and the read-modify-write cycle. the falling edge of we or lcas /ucas , whichever is later, serves as the input data-latch strobe. in the early write cycle, the input data of dq 1 -dq 8 are strobed by lcas and dq 9 -dq 16 are strobed by ucas and the setup/hold times are referenced to each falling edge of lcas and ucas because we goes low before lcas/ucas. in the delayed write or read-modify-write cycle, we goes low after lcas /ucas ; thus, input data is strobed by we and all setup/hold times are referenced to the falling edge of we . since this device is an i/ o common type, when the delayed write or read-modi?d-write is executed, i/o data have to be controlled by oe . data output the three-state buffers are ttl compatible with a fanout of two ttl loads. polarity of the output data is identical to that of the input; the output buffers remain in the high-impedance state until the column address strobe goes low. when a read or read-modify-write cycle is executed, valid outputs are obtained under the following conditions: t rac : from the falling edge of ras when t rcd (max) is satis?d. t cac : from the falling edge of lcas (for dq 1 -dq 8 ) ucas (for dq 9 -dq 16 ) when t rcd is greater than t rcd (max). t aa : from column address input when t rad is greater than t rad (max). t oea : from the falling edge of oe when oe is brought low after t rac , t cac , or t aa . the data remains valid until either lcas /ucas or oe returns to a high logic level. when an early write is executed, the output buffers remain in a high-impedance state during the entire cycle. parameter notes symbol min. typ. max. unit ambient operating temp supply voltage v cc 4.5 5.0 5.5 v 0 c to +70 c v ss 00 0 input high voltage, all inputs v ih 2.4 6.5 v input low voltage, all inputs(*) v il ?.3 0.8 v input low voltage, dq(*) v ild ?.3 0.8 v 1 1 1 1
6 mb814260-60/MB814260-70 fast page mode of operation the fast page mode of operation provides faster memory access and lower power dissipation. the fast page mode is implemented by keeping the same row address and strobing in successive column addresses. to satisfy these conditions, ras is held low for all contiguous memory cycles in which row addresses are common. for each fast page of memory, any of 512 16-bits can be accessed. fast page mode operations need not be addressed sequentially and combinations of read, write, and/or ready-modify-write cycles are permitted.
7 mb814260-60/MB814260-70 n dc characteristics (recommended operating conditions unless otherwise noted.) notes 3 parameter notes symbol conditions value unit min. max. output high voltage v oh i oh = ? ma 2.4 v output low voltage v ol i ol = 4.2 ma 0.4 input leakage current (any input) i i(l) 0 v v in 5.5 v; 4.5 v v cc 5.5 v; v ss = 0 v; all other pins not under test = 0 v ?0 10 m a output leakage current i dq(l) 0 v v out 5.5 v; data out disabled ?0 10 operating current (average power supply current) mb814260-60 i cc1 ras & lcas , ucas cycling; t rc = min 95 ma MB814260-70 84 standby current (power supply current) ttl level i cc2 ras = lcas , ucas = v ih 2.0 ma cmos level ras = lcas , ucas 3 v cc ?.2 v 1.0 refresh current #1 (average power supply current) mb814260-60 i cc3 lcas , ucas = v ih , ras cycling; t rc = min 95 ma MB814260-70 84 fast page mode current mb814260-60 i cc4 ras = v il , lcas , ucas cycling; t pc = min 95 ma MB814260-70 84 refresh current #2 (average power supply current) mb814260-60 i cc5 ras cycling; cas -before-ras ; t rc = min 95 ma MB814260-70 84 1 1 2 2 2 2
8 mb814260-60/MB814260-70 n ac characteristics (at recommended operating conditions unless otherwise noted.) notes 3, 4, 5 (continued) no. parameter notes symbol mb814260-60 MB814260-70 unit min. max. min. max. 1 time between refresh t ref 8.2 8.2 ms 2 random read/write cycle time t rc 110 125 ns 3 read-modify-write cycle time t rwc 150 170 ns 4 access time from ras t rac ?0?0ns 5 access time from cas t cac ?0?0ns 6 column address access time t aa ?0?5ns 7 output hold time t oh 0?ns 8 output buffer turn on delay time t on 0?ns 9 output buffer turn off delay time t off ?5?5ns 10 transition time t t 250250ns 11 ras precharge time t rp 40?5ns 12 ras pulse width t ras 60 100000 70 100000 ns 13 ras hold time t rsh 20?0ns 14 cas to ras precharge time t crp 0?ns 15 ras to cas delay time t rcd 20 40 20 50 ns 16 cas pulse width t cas 20 10000 20 10000 ns 17 cas hold time t csh 60?0ns 18 cas precharge time (normal) t cpn 10?0ns 19 row address setup time t asr 0?ns 20 row address hold time t rah 10?0ns 21 column address setup time t asc 0?ns 22 column address hold time t cah 12?2ns 23 ras to column address delay time t rad 15 30 15 35 ns 24 column address to ras lead time t ral 30?5ns 25 column address to cas lead time t cal 30?5ns 26 read command setup time t rcs 0?ns 27 read command hold time referenced to ras t rrh 0?ns 28 read command hold time referenced to cas t rch 0?ns 29 write command setup time t wcs 0?ns 30 write command hold time t wch 10?0ns 31 we pulse width t wp 10?0ns 32 write command to ras lead time t rwl 15?0ns 6, 9 7, 9 8, 9 10 11, 12 19 13 14 14 15
9 mb814260-60/MB814260-70 n ac characteristics (continued) (at recommended operating conditions unless otherwise noted.) notes 3, 4, 5 no. parameter notes symbol mb814260-60 MB814260-70 unit min. max. min. max. 33 write command to cas lead time t cwl 15?8ns 34 din setup time t ds 0?ns 35 din hold time t dh 10?0ns 36 ras to we delay time t rwd 85?5ns 37 cas to we delay time t cwd 40?0ns 38 column address to we delay time t awd 55?0ns 39 ras precharge time to cas active time (refresh cycles) t rpc 10?0ns 40 cas set up time for cas -before-ras refresh t csr 0?ns 41 cas hold time for cas -before-ras refresh t chr 10?0ns 42 access time from oe t oea ?0?0ns 43 output buffer turn off delay from oe t oez ?5?5ns 44 oe to ras lead time for valid data t oel 10?0ns 45 oe hold time referenced to we t oeh 0?ns 46 oe to data in delay time t oed 15?5ns 47 din to cas delay time t dzc 0?ns 48 din to oe delay time t dzo 0?ns 50 column address hold time from ras t ar 32?2ns 51 write command hold time from ras t wcr 30?0ns 52 din hold time referenced to ras t dhr 30?0ns 53 cas to data in delay time t cdd 15?5ns 60 fast page mode ras pulse width t rasp 60 200000 70 200000 ns 61 fast page mode read/write cycle time t pc 40?5ns 62 fast page mode read-modify-write cycle time t prwc 80?0ns 63 access time from cas precharge t cpa ?5?0ns 64 fast page mode cas pulse width t cp 10?0ns 65 fast page mode ras hold time from cas precharge t rhcp 35?0ns 66 fast page mode cas precharge to we delay time t cpwd 55?0ns 9 10 16 17 17 9, 18
10 mb814260-60/MB814260-70 notes: 1. referenced to v ss . to all v cc (v ss ) pins, the same supply voltage should be applied. 2. i cc depends on the output load conditions and cycle rates; the speci?d values are obtained with the output open. i cc depends on the number of address change as ras = v il and ucas = v ih , lcas = v ih , v il > ?.3v. i cc1 , i cc3 and i cc5 are speci?d at one time of address change during ras = v il and ucas = v ih , lcas = v ih . i cc4 is speci?d at one time of address change during one page cycle. 3. an initial pause (ras = cas = v ih ) of 200 m s is required after power-up followed by any eight ras - only cycles before proper device operation is achieved. in case of using internal refresh counter, a minimum of eight cas -before-ras initialization cycles instead of 8 ras cycles are required. 4. ac characteristics assume t t = 5 ns. 5. v ih (min.) and v il (max.) are reference levels for measuring timing of input signals. also transition times are measured between v ih (min.) and v il (max.). 6. assumes that t rcd t rcd (max.), t rad t rad (max.). if t rcd is greater than the maximum recommended value shown in this table, t rac will be increased by the amount that t rcd exceeds the value shown. refer to fig. 2 and 3. 7. if t rcd 3 t rcd (max.), t rad 3 t rad (max.), and t asc 3 t aa ?t cac ?t t , access time is t cac . 8. if t rad 3 t rad (max.) and t asc t aa ?t cac ?t t , access time is t aa . 9. measured with a load equivalent to two ttl loads and 100 pf. 10. t off and t oez is speci?d that output buffer change to high impedance state. 11. operation within the t rcd (max.) limit ensures that t rac (max.) can be met. t rcd (max.) is speci?d as a reference point only; if t rcd is greater than the speci?d t rcd (max.) limit, access time is controlled exclusively by t cac or t aa . 12. t rcd (min.) = t rah (min.) + 2t t + t asc (min.). 13. operation within the t rad (max.) limit ensures that t rac (max.) can be met. t rad (max.) is speci?d as a reference point only; if t rad is greater than the speci?d t rad (max.) limit, access time is controlled exclusively by t cac or t aa . 14. either t rrh or t rch must be satis?d for a read cycle. 15. t wcs is speci?d as a reference point only. if t wcs 3 t wcs (min.) the data output pin will remain high-z state through entire cycle. 16. assumes that t wcs < t wcs (min.). 17. either t dzc or t dzo must be satis?d. 18. t cpa is access time from the selection of a new column address (that is caused by changing both ucas and lcas from ? to ??. therefore, if t cp is long, t cpa is longer than t cpa (max.). 19. assumes that cas -before-ras refresh.
11 mb814260-60/MB814260-70 n functional truth table x; ? or ? *; it is impossible in fast page mode. operation mode clock input address input/output data refres h note ras lca s uca s we oe row col- umn dq 1 to dq 8 dq 9 to dq 16 input output input output standby h h h x x high-z high-z read cycle l l h l h l l h l valid valid valid high-z valid high-z valid valid yes* t rcs 3 t rcs (min.) write cycle (early write) l l h l h l l l x valid valid valid valid high-z valid valid high-z yes* t wcs 3 t wcs (min.) read-modify- write cycle l l h l h l l h ? ll ? h valid valid valid valid valid high-z valid valid valid high-z valid valid yes* ras -only refresh cycle l h h x x valid high-z high-z yes cas -before- ras refresh cycle l l l x x high-z high-z yes t csr 3 t csr (min.) hidden refresh cycle h ? l l h l h l l hl valid high-z valid high-z valid valid yes previous data is kept. fig. 2 ? t rac vs. t rcd fig. 3 ? t rac vs. t rad fig. 4 ? t cpa vs. t cp t rac (ns) t rcd (ns) t rac (ns) t rad (ns) t cpa (ns) t cp (ns) 140 120 100 80 60 20 60 80 100 70ns version 40 100 90 80 70 20 40 50 60 70ns version 30 00 70 60 50 40 10 30 40 50 20 0 60ns version 60 60ns version 30 70ns version 60ns version
12 mb814260-60/MB814260-70 t cah fig. 5 ? read cycle description to implement a read operation, a valid address is latched in by the ras and lcas or ucas address strobes and with we set to a high level and oe set to a low level, the output is valid once the memory access time has elapsed. lcas controls the input/ output data on dq 1 -dq 8 pins, ucas controls one on dq 8 -dq 16 pins. the access time is determined by ras (t rac ), lcas /ucas (t cac ), oe (t oea ) or column addresses (t aa ) under the following conditions: if t rcd > t rcd (max.), access time = t cac . if t rad > t rad (max.), access time = t aa . if oe is brought low after t rac , t cac , or t aa (whichever occurs later), access time = t oea . however, if either lcas /ucas or oe goes high, the output returns to a high-impedance state after t oh is satis?d. ? or row add valid data high-z high-z column add t crp t rc t ras t rp t rcd t csh t rsh t cas ras v ih v il v ih v il v ih v il v ih v il v oh v ol we dq (output) a 0 to a 8 v ih v il dq (input) v ih v il oe t cdd t asr t rah t asc t rad t ral t cal t oel t rch t rrh t rcs t oh t off t aa t cac t rac t ar t dzc t dzo t on t oed t oh t on t oez t oea lcas or ucas
13 mb814260-60/MB814260-70 fig. 6 ? early write cycle (oe = ? or ?? description a write cycle is similar to a read cycle except we is set to a low state and oe is an ? or ? signal. a write cycle can be implemented in either of three ways ?early write, oe write (delayed write), or read-modify-write. during all write cycles, timing parameters t rwl , t cwl , t ral and t cal must be satis?d. in the early write cycle shown above t wcs satis?d, data on the dq pins are latched with the falling edge of lcas or ucas and written into memory. ? or row valid data i n add column add high-z ras v ih v il v ih v il v ih v il v ih v il v ih v il we dq (input) a 0 to a 8 v oh v ol dq (output) t rp t rc t ras t rcd t crp t cas t csh t rsh t asr t cah t ar t rah t wcs t ral t wch t cal t rad t ds t dh t wcr t dhr t asc lcas or ucas
14 mb814260-60/MB814260-70 lcas or ucas fig. 7 ? oe (delayed write) cycle ras v ih v il v ih v il v ih v il v ih v il v ih v il we dq (input) a 0 to a 8 v oh v ol dq (output) v ih v il oe description in the oe (delayed write) cycle, t wcs is not satis?d; thus, the data on the dq pins is latched with the falling edge of we and written into memory. the output enable (oe ) signal must be changed from low to high before we goes low (t oed + t t + t ds ). ? or invalid data valid data i n col row add add high-z high-z high-z t asc t rp t rc t ras t rcd t crp t asr t cah t rah t rad t csh t cas t rsh t cal t ral t rwl t ar t cwl t wp t wch t dzc t oed t dh t dzo t oeh t oez t cac t rac t aa t ds t wcr t oea t dhr
15 mb814260-60/MB814260-70 lcas or ucas fig. 8 ? read-modify-write cycle ras v ih v il v ih v il v ih v il v ih v il v ih v il we dq (input) a 0 to a 8 v oh v ol dq (output) v ih v il oe description the read-modify-write cycle is executed by changing we from high to low after the data appears on the dq pins. in the read- modify-write cycle, oe must be changed from low to high after the memory access time. ? or valid data i n col row add add high-z high-z valid high-z t asc t rp t rwc t ras t rcd t crp t asr t cah t rah t rad t csh t cas t rsh t ral t ds t rwl t rcs t cwl t dh t cwd t wp t rwd t awd t wcr t dzc t oed t dzo t oeh t oez t dhr t cac t rac t aa t on t oea t ar t on
16 mb814260-60/MB814260-70 t rcd fig. 9 ? fast page mode read cycle ras v ih v il v ih v il v ih v il v ih v il v ih v il we dq (input) a 0 to a 8 v oh v ol dq (output) v ih v il oe description the fast page mode of operation permits faster successive memory operations at multiple column locations of the same row address. this operation is performed by strobing in the row address and maintaining ras at a low level and we at a high level during all successive memory cycles in which the row address is latched. the access time is determined by t cac , t aa , t cpa , or t oea , whichever one is the latest in occurring. ? or valid data col row add add col add high-z high-z high-z high-z t cas t rhcp t crp t rasp t rp t cas t rsh t rrh t cdd t pc t csh t rad t cp t asr t asc t cah t cah t asc t oel t cah t asc t ral t rch t rah t cal t rcs t rch t rch t dzc t cpa t oed t cdd t oh t dzc t dzc t rcs t rcs t ar t on t oh t cac t on t cac t on t dzo t rac t off t dzo t aa t oez t oea t oh t oh t aa t oed t off t oea t oez t dzo lcas or ucas col add t cas
17 mb814260-60/MB814260-70 fig. 10 ? fast page mode write cycle (oe = ? or ?? ras v ih v il v ih v il v ih v il v ih v il we a 0 to a 8 description the fast page mode write cycle is executed in the same manner as the fast page mode read cycle except the states of we and oe are reversed. data appearing on the dq 1 to dq 8 is latched on the falling edge of lcas and one appearing on the dq 9 to dq 16 is latched on the falling edge of ucas and the data is written into the memory. during the fast page mode write cycle, including the delayed (oe ) write and read-modify-write cycles, t cwl must be satis?d. ? or ? v ih v il dq (input) v oh v ol dq (output) lcas or ucas high-z t rasp t rcd t cp t cas t csh t pc t dhr t wcr t ar t crp t cas t cas t rp t rsh t rhcp t cah t ral t cah t asc t asr t asc t asc t cah t rah t rad t cal t wch t wcs t wch t wcs t cwl t wcl t wcs t wch t wcl t wp t ds t dh t wp t wp t ds t ds t dh t dh t rwl col row add add col add col add valid data valid data valid data
18 mb814260-60/MB814260-70 ? or ? invalid data fig. 11 ? fast page mode oe write cycle description the fast page mode oe (delayed) write cycle is executed in the same manner as the fast page mode write cycle except for the states of we and oe . input data on the dq pins are latched on the falling edge of we and written into memory. in the fast page mode delayed write cycle, oe must be changed from low to high before we goes low (t oed + t t + t ds ). dq (input) dq (output) ras v ih v il v ih v il v ih v il v ih v il v ih v il we a 0 to a 8 v oh v ol v ih v il oe lcas or ucas t rcs col row add. add col add valid valid valid high-z col add t rasp t rad t crp t rcd t cas t cp t pc t csh t cas t rp t cas t rsh t cah t asc t ral t cah t asc t cah t rah t asc t cal t wp t rwl t wcr t cwl t wch t wp t wp t ar t cwl t cwl t wch t wch t ds t dh t dhr t dzc t dh t ds t dh t ds t aa t oea t oeh t oea t cac t rac t oed t aa t cac t aa t oed t cac t oeh t oeh t oed t oea t dzo t oez t oez t oez t asr
19 mb814260-60/MB814260-70 ? or ? valid data fig. 12 ? fast page mode read-modify-write cycle description during fast page mode of operation, the read-modify-write cycle can be executed by switching we from high to low after input date appears at the dq pins during a normal cycle. dq (input) dq (output) v ih v oh ras v ih v il v ih v il v ih v il v ih v il we a 0 to a 8 v ol v ih v il oe v il lcas or ucas t on valid valid valid col row add add col add col add high-z wch t t crp t rasp t rcd t rad t cas t cp t prwc t csh t rp t cas t cas t rsh t asc t cah t asr t rah t asc t cah t asc t cah t wch t wch t ral t cwl t rcs t rcs t wp t cwl t cwl t wp t rcs t cpwd t wp t rwl t ar t dzc t awd t dh t cwd t dhr t ds t ds t ds t dh t dh t oed t oed t cac t aa t aa t cac t cwd t on t oeh t on t dzo t oea t cpa t on t oez t oez t oea t wcr
20 mb814260-60/MB814260-70 fig. 13 ? ras -only refresh (we = oe = ? or ?? description refresh of ram memory cells is accomplished by performing a read, a write, or a read-modify-write cycle at each of 512 row addresses every 8.2-milliseconds. three refresh modes are available: ra s-only refresh, cas -before-ras refresh, and hidden refresh. ras -only refresh is performed by keeping ras low and lcas and uca s high throughout the cycle; the row address to be refreshed is latched on the falling edge of ras . during ras -only refresh, dq pins are kept in a high-impedance state. ? or high-z row address v ih v il ras v ih v il v ih v il a 0 to a 9 dq (output) v oh v ol t rc t rp t asr t rpc t rah t oh t ras t off t crp lcas and ucas high-z t cpn t csr t chr t rpc fig. 14 ? cas -before-ras refresh (addresses = we = oe = ? or ?? dq (output) ras v ih v il v ih v il v oh v ol description cas -before-ras refresh is an on-chip refresh capability that eliminates the need for external refresh addresses. if lcas or ucas is held low for the speci?d setup time (t csr ) before ras goes low, the on-chip refresh control clock generators and refresh address counter are enabled. an internal refresh operation automatically occurs and the refresh address counter is internally incremented in preparation for the next cas -before-ras refresh operation. ? or t rc t ras t rp t off t oh lcas and ucas
21 mb814260-60/MB814260-70 fig. 15 ? hidden refresh cycle description a hidden refresh cycle may be performed while maintaining the latest valid data at the output by extending the active time of lcas or ucas and cycling ras . the refresh row address is provided by the on-chip refresh address counter. this eliminates the need for the external row address that is required by drams that do not have cas -before-ras refresh capability. ? or dq (input) dq (output) ras v ih v il v ih v il v ih v il v ih v il v ih v il we a 0 to a 8 v oh v ol v ih v il oe column row address address valid data out high-z t cah t rc t rp t chr t rc t ras t ras t rp t oel t rsh t rad t rcd t asc t asr t ral t crp t ar t rcs t rrh t cdd t cac t dzc t aa t dzo t oea t oed t off t on t oh t rac t on t rah high-z lcas or ucas t oez t oh
22 mb814260-60/MB814260-70 fig. 16 ? cas -before-ras refresh counter test cycle (at recommended operating conditions unless otherwise noted.) note: assumes that cas -before-ras refresh counter test cycle only. v ih v il v ih v il ras a 0 to a 8 v ih v il v ih v il v ih v il v oh v ol v ih v il we dq (input) oe description a special timing sequence using the cas -before-ras refresh counter test cycle provides a convenient method to verify the functionality of cas -before-ras refresh circuitry. after a cas -before-ras refresh cycle, if lcas or ucas makes a transition from high to low while ras is held low, read and write operations are enabled as shown above. row and column addresses are de?ed as follows: row address: bits a 0 through a 8 are de?ed by the on-chip refresh counter. column address: bits a 0 through a 8 are de?ed by latching levels on a 0 -a 8 at the second falling edge of lcas or ucas . the cas -before-ras counter test procedure is as follows ; 1) normalize the internal refresh address counter by using 8 ras only refresh cycles. 2) use the same column address throughout the test. 3) write ? to all 512 row addresses at the same column address by using cbr refresh counter test cycles. 4) read ? written in procedure 3) by using normal read cycle and check; after reading ? and check are completed (or simultaneously), write ? to the same addresses by using normal write cycle (or read-modify-write cycle). 5) read and check data ? written in procedure 4) by using cbr refresh counter test cycle for all 512 memory locations. 6) reverse test data and repeat procedures 3), 4), and 5). dq (output) cas to we delay time parameter unit min. max. ns no. min. max. 90 60 55 symbol 91 30 ns 30 column address hold time 92 cas pulse width 93 ras hold time 80 ns 80 55 ns 55 94 55 ns 55 ?s 85 85 cas hold time 95 mb814260-60 MB814260-70 access time from cas t fcac t fcah t fcwd t fcas t fcsh t frsh lcas or ucas t on t fcwd ? or ? valid data high-z high-z high-z valid data in column address t rp t frsh t fcas t fcsh t chr t csr t cp t asc t ral t ar t fcah t rcs t rwl t wcr t dh t wp t ds t dzc t oed t fcac t oea t dzo t oez t oeh t dhr t cwl t cdd
23 mb814260-60/MB814260-70 n package dimensions (suf?: -pj) 40 pin, plastic soj (lcc-40p-m01) dimensions in mm (inches). * : this dimension exclude resin protrusion(each side:.006(0.15)max.). 26.030.13(1.0250.05) 3.50 +0.25 ?0.20 +.010 ?.008 .138 .008 ?.001 +.002 ?0.02 +0.05 0.20 (.370.020) 9.400.51 r0.89(.035)typ 0.64(.025)min 2.31(.091)nom 0.81(.032)max. 0.430.10(.017.004) details of "a" part 2.60(.102)nom 0.10(.004) index 20 21 40 1 1.270.13 (.050.005) 24.13(.950)ref (.440.005) 11.180.13 nom 10.16(.400) * "a" lead no 1995 fujitsu limited c40051s-3c-1 c
24 mb814260-60/MB814260-70 n package dimensions (continued) (suf?: -pftn) 44 pin, plastic tsop (ii) (fpt-44p-m07) dimensions in mm (inches). * : this dimension exclude resin protrusion(each side : .006(0.15) max). +0.10 C0.05 +.004 C.002 35 44 32 23 22 13 * 0.25(.010) 0.15(.006) 0.40(.016)max 0.15(.006)max lead no. index "a" 1 10 (.006.002) 0.150.05 (.424.008) 10.760.20 (.020.004) 0.500.10 (.463.008) 11.760.20 (.400.004) 10.160.10 1.10 .043 (stand off) 0(0)min 0.10(.004) 16.80(.661)ref 0.80(.0315)typ 0.13(.005) m (.725.004) 18.410.10 (.012.004) 0.300.10 details of "a" part 1994 fujitsu limited f44016s-1c-2 c
25 mb814260-60/MB814260-70 n package dimensions (continued) (suf?: -pftr) 44 pin, plastic tsop (ii) (fpt-44p-m08) dimensions in inches (millimeters) * : this dimension exclude resin protrusion(each side : .006(0.15) max.). +0.10 C0.05 +.004 C.002 35 44 32 23 22 13 * 0.25(.010) 0.15(.006) 0.40(.016)max 0.15(.006)max lead no. index "a" 1 10 (.006.002) 0.150.05 (.424.008) 10.760.20 (.020.004) 0.500.10 (.463.008) 11.760.20 (.400.004) 10.160.10 1.10 .043 (stand off) 0(0)min 0.10(.004) 16.80(.661)ref 0.80(.0315)typ 0.13(.005) m (.725.004) 18.410.10 (.012.004) 0.300.10 details of "a" part 1994 fujitsu limited f44017s-1c-2 c
26 mb814260-60/MB814260-70 all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales representatives before ordering. the information and circuit diagrams in this document presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. also, fujitsu is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. fujitsu semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). caution: customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with fujitsu sales representatives before such use. the company will not be responsible for damages arising from such use without prior approval. any semiconductor devices have inherently a certain rate of failure. you must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on export under the foreign exchange and foreign trade control law of japan, the prior authorization by japanese government should be required for export of those products from japan. fujitsu limited for further information please contact: japan fujitsu limited corporate global business support division electronic devices kawasaki plant, 4-1-1, kamikodanaka nakahara-ku, kawasaki-shi kanagawa 211-88, japan tel: (044) 754-3753 fax: (044) 754-3329 north and south america fujitsu microelectronics, inc. semiconductor division 3545 north first street san jose, ca 95134-1804, u.s.a. tel: (408) 922-9000 fax: (408) 432-9044/9045 europe fujitsu mikroelektronik gmbh am siebenstein 6-10 63303 dreieich-buchschlag germany tel: (06103) 690-0 fax: (06103) 690-122 asia paci? fujitsu microelectronics asia pte. limited #05-08, 151 lorong chuan new tech park singapore 556741 tel: (65) 281 0770 fax: (65) 281 0220 f9703 ? fujitsu limited printed in japan

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